1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a semiconductor memory device in which high-speed access can be made even if integration density is increased.
2. Description of the Prior Art
FIG. 1 is a block diagram showing the entire structure of a conventional collectively erasable type of electrically erasable and programmable read-only memory (referred to as flush EEPROM hereinafter).
In FIG. 1, the flush EEPROM includes a plurality of memory cell arrays 31. Each of the memory cell arrays 31 is provided with a column decoder/Y gate 32. In addition, the plurality of memory cell arrays 31 are provided with a common row decoder 33. A column address signal is applied to the plurality of column decoder/Y gates 32 from a Y address buffer 34. A row address signal is applied to the row decoder 33 from an X address buffer 35. On the other hand, sense amplifier/write drivers 36 are connected to the column decoder/Y gates 32 through I/O lines I/O, respectively. A common input/output buffer 37 is connected to the plurality of sense amplifier/write drivers 36.
A chip enable signal CE, a write enable signal WE and an output enable signal OE.pi.are externally applied to a control signal input buffer 38. The control signal input buffer 38 is responsive to the signals for applying a control signal to a write/read timing generating circuit 39. The write/read timing generating circuit 39 is responsive to this control signal for generating various timing signals, to control a writing operation and a reading operation.
Each of the memory cell arrays 31 includes a plurality of memory cells arranged in a matrix as described below. The row decoder 33 is responsive to the row address signal applied from the X address buffer 35 for selecting one row in the memory cell arrays 31. The column decoder/Y gates 32 are responsive to the column address signal applied from the Y address buffer 34 for selecting columns in the memory cell arrays 31, respectively Data are read out from memory cells respectively provided at intersections of the rows and the columns, amplified by respective sense amplifiers in the sense amplifier/write drivers 36, and outputted through the input/output buffer 37.
FIG. 2 is a circuit diagram showing a structure of one of the memory cell arrays 31 included in the flush EEPROM shown in FIG. 1.
In FIG. 2, a plurality of memory cells MC are arranged in a matrix in the memory cell array 31. A bit line BL is arranged in each column of the plurality of memory cells MC. The memory cells MC have their drains connected to the bit line BL. The bit lines BL are connected to an I/O line I/O through N channel MOS transistors Q31, respectively. The plurality of transistors Q31 constitute a Y gate included in each of the column decoder/Y gates 32 shown in FIG. 1. Each of the transistors Q31 has its gate connected to a column decoder 32a included in each of the column decoder/Y gates 32. In addition, a word line WL is provided in each row of the plurality of memory cells MC. The memory cells MC have their control gates connected to the word line WL. A plurality of word lines WL are connected to a row decoder 33. All the memory cells MC have their sources connected to ground through a source line SL and an N channel MOS transistor Q32. The transistor Q32 has its gate receiving an erase signal ERS. On the other hand, a current detecting type sense amplifier 40 included in each of the sense amplifier/write drivers 36 is connected to the I/O line I/O.
FIG. 3 is a cross sectional view showing a memorY transistor constituting a memory cell MC, and FIG. 4 is a diagram showing an equivalent circuit of the memory transistor.
The memory transistor comprises a source 41, a drain 42, a floating gate 43 and a control gate 44. Data "1" or "0" is stored in the memory transistor depending on whether or not electrons are stored in the floating gate 43. More specifically, when electrons are stored in the floating gate 43, the threshold voltage of the memory transistor becomes high. Consequently, if and when a predetermined voltage is applied to the control gate 44, a path between the source 41 and the drain 42 is rendered non-conductive. Contrary to this, when electrons are emitted from the floating gate 43, the threshold voltage of the memory transistor becomes low. Consequently, if a predetermined voltage is applied to the control gate 44, the path between the source 41 and the drain 42 is rendered conductive. Thus, an on or off state of the memory transistor corresponds to data "0" or "1" to be stored.
Description is now made on an erasing operation, a writing operation and a reading operation of the flush EEPROM shown in FIG. 2.
In the erasing operation, as shown in FIG. 5A, a high voltage V.sub.PP is applied to all the bit lines BL, and all the word lines WL are grounded. On this occasion, the erase signal ERS is brought to an "L" level, so that the transistor Q32 is rendered non-conductive, whereby the source line SL remains electrically floating. Consequently, as shown in FIG. 5B, electrons stored in the floating gate 43 in the memory transistor are emitted into the drain 42 by a tunnel phenomenon. As a result, the threshold voltage of the memory transistor becomes low. In the above described manner, data stored in all the memory cells MC are simultaneously erased.
In the writing operation, as shown in FIG. 6A, the high voltage V.sub.PP is applied to a selected bit line BL and a selected word line WL. On this occasion, the erase signal ERS is brought to an "H" level. As a result, the transistor Q32 is turned on, so that the source line SL is grounded. Consequently, as shown in FIG. 6B, avalanche breakdown occurs in the vicinity of the drain 42 in the memory transistor, so that hot electrons are injected into the floating gate 43. Therefore, the threshold voltage of the memory transistor becomes high. In the above described manner, data is written to a memory cell MC enclosed by a broken line in FIG. 6A.
Description is now made on the reading operation of the flush EEPROM. In FIG. 2, any of the plurality of word lines WL is selected by the row decoder 33, so that an "H" level potential is applied to the word line. In addition, any of the plurality of transistors Q31 is selected by the column decoder 32a, so that the "H" level potential is applied to a gate of the selected transistor. Thus, one memory cell MC is selected. The current detecting type sense amplifier 40 connected to the I/O line I/O determines whether or not a current flows from a drain to a source of the selected memory cell MC.
FIG. 7 is a circuit diagram showing the current detecting type amplifier 40 shown in FIG. 2. The current detecting type sense amplifier 40 is disclosed in, for example, Japanese Patent Laying-Open Gazette No. 170097/1987.
The sense amplifier 40 comprises a current-voltage converting circuit 40a for converting to a voltage signal a current corresponding to data stored in a memory cell MC, and an inverter circuit 40b for inverting the converted voltage signal. The current-voltage converting circuit 40a comprises P channel MOS transistors Q41 and Q42 and N channel MOS transistors Q43, Q44 and Q45.
First, in the reading operation, when the memory cell MC is rendered conductive, a potential of a node N11 becomes approximately 1.0 V in a steady state. Consequently, the transistor Q43 is slightly turned on, so that a potential of a node N12 becomes approximately 2 V. Therefore, the transistors Q44 and Q45 are slightly turned on. However, since the on-resistance of the transistor Q42 is set to be larger than that of the transistor Q45, a potential of a node N13 becomes approximately the same (i.e., 1.0 V) as the potential of the node N11.
Then, in the reading operation, when the memory cell MC is rendered non-conductive, the potential of the node N11 becomes approximately 1.1 V. Consequently, the potential of the node N12 becomes approximately 1.8 V, so that the potential difference between a gate and a source of each of the transistors Q44 and Q45 becomes approximately 0.7 V. Thus, the transistors Q44 and Q45 are turned off, so that the potential of the node N13 is pulled up to 5 V.
When the size of a memory cell is decreased as the semiconductor memory device is made finer and the integration density thereof is increased, a current (cell current) flowing through the memory cell is reduced. In order to detect this reduced cell current, the sensitivity of the current detecting type sense amplifier must be increased. However, when the size of a load transistor, (for example, the transistor Q42 shown in FIG. 7) in the sense amplifier is decreased in order to increase the sensitivity of the sense amplifier, the access time is delayed, so that the reading operation is not speeded up.
On the other hand, Japanese Patent Laying-Open Gazette No. 73300/1986 discloses a semiconductor memory device using a differential amplifier circuit. In this semiconductor memory device, a pair of bit lines 51 and 52 are connected to both sides of a differential amplifier circuit 59, as shown in FIG. 8. A plurality of memory cells 55A (only one memory cell is illustrated in FIG. 8) and one dummy cell 58A are connected to the bit line 51, and a plurality of memory cells 55B (only one memory cell is illustrated in FIG. 8) and one dummy cell 58B are connected to the bit line 52.
At the time of the reading operation, the bit lines 1 and 52 are charged to a power-supply potential V.sub.DD When one of the memory cells 55A connected to the bit line 1 is selected, the dummy cell 58B connected to the bit line 52 is simultaneously selected. Consequently, if data "1" is stored in the selected memory cell 55A, a potential on the bit line 51 remains at the power-supply potential V.sub.DD. On the contrary, if data "0" is stored in the selected memory cell 55A, the bit line 51 is discharged to a ground potential. On the other hand, respective conductances of the dummy cells 58A and 58B are set smaller than those of the memory cells 55A and 55B storing data "0" and larger than those of the memory cells 55A and 55B storing data "1". Thus, when the dummy cell 58B is selected, the bit line 52 is discharged. The change in potential on the bit line 52 becomes gentler than that appearing when data "0" is read out to the bit line 51. Consequently, a potential difference appears between the bit lines 51 and 52. This potential difference is differentially amplified by the differential amplifier circuit 59.
In this semiconductor memory device, since the current detecting type sense amplifier is not employed unlike the conventional flush EEPROM shown in FIGS. 1 and 2, the above described problems do not occur.
However, in the semiconductor memory device shown in FIG. 8, the respective conductances of the dummy cells 58A and 58B must be set to one-half of the respective conductances of the memory cells 55A and 55B. Such setting of parameters of the dummy cells 58A and 58B involves difficulty in manufacturing techniques.
Furthermore, in the semiconductor memory device shown in FIG. 8, one differential amplifier circuit 59 is provided for each pair of bit lines 51 and 52. Therefore, when a pitch between the bit lines is decreased as the semiconductor memory device is made finer and the integration density thereof is increased, a space becomes small in which the differential amplifier circuit 59 is arranged, so that the layout becomes difficult.
Additionally, in the semiconductor memory device shown in FIG. 8, the bit lines 51 and 52 are precharged to the power-supply potential V.sub.DD (about 5 V) before reading out data. Consequently, the power-supply potential V.sub.DD is applied to respective drains of the memory cells 55A and 55B, so that the potential difference between a floating gate storing electrons and the drains is increased. As a result, electrons are liable to be emitted from the floating gate to the drains by the tunnel phenomenon, whereby data holding characteristics of the memory cells 55A and 55B ar liable to be adversely affected.